Method and arrangement for checking the conformity of signals with a code system



May 28, 1963 H. REICHERT METHOD AND ARRANGEMENT FOR CHECKING THECONFORMI 0F SIGNALS WITH A 000E SYSTEM Filed April 10, 1961 LULOLOLOLOLUULLOOLLO OLLLLOOOOL LLl-LLOOOOO LLLLLOUUOO OOOOOLLLLL 123 5678LULOLOLOLO LUOLLOOLLO LLLLUOOUL UODOOLLLLL 0 23456789 QQQ N Jib 1NUnited States Patent 3,091,391 METHOD AND ARRANGEMENT FGR CHECKENG THECONFORMITY OF SIGNALS WITH A CODE SYSTEM Hugo Reichert, Wilhelmsiiaven,Germany, assignor to Olympia Werke AG, Wilhelmshaven, Germany Filed Apr.10, 1961, Ser. No. 101,827 Claims priority, application Germany Apr. 11,1960 9 Claims. (Cl. 235-153) The present invention concerns a method anda circuit arrangement for the purpose of checking, in the course ofprocessing coded digital information, whether the various signalcombinations which are being introduced are in conformity with the termsof a selected portion of the particular code system. More particularly,the invention applies to the processing of information represented bysignal combinations in terms of e.g. a binary code, wherein digitalinformation is represented by a binary-decimal eX- cess-code.

It is to be understood that a binary-decimal code system represents eachof the digits in the different decimal orders of a multi-order decimalnumber by a separate binary bit combination. The characteristics of anexcess-code system will be explained further below in reference to thedrawing.

In the development of electronic calculating machines it is oftendesirable to provide for a method and for a circuit arrangement whichmakes it possible to check on digital information being processed by themachine, and particularly to check whether at certain points within thenetwork of the machine the coded information appearing at such points iscomposed of bit combinations representing certain information inconformity with the particular code system. It is further desirable thatupon the appearance of a bit combination which is not one of the bitcombinations which represent according to the code system such specificinformation, a suitable indication or error signal is produced and/orsome corresponding operational function of a machine component iseffected. Such a checking on the coded information introduced into adata processing machine is of particular importance where theinformation is of alphanumeric character because under suchcircumstances it is necessary to differentiate clearly between bitcombinations representing, according to the particular code system,digits that are further to be processed in the machine and representedby the respective excess code, and, on the other hand, similarly codedalphabetical information which could not be processed in the same mannerand is not to be processed in the same way by the machine or by thecalculating portion of the machine.

It would be possible to provide for checking means which comprise e.g. aseparate checking channel for every one of the ten bit-combinationswhich according to the code system represent respectively the digitsranging from 0 to 9. However such an arrangement would call for anexcessively large number of lines and control elements, particularly inthe case of a code system providing for every one of the digits a greatnumber of code elements, as for instance in the case of a 6-elementcode, an 8-element code, etc. It would be also possible to add to everyone of the various bit combinations of the code a separate check-bit.The relation of such check-bit to the other bits of each bitcombination, if tested by the checking means, would indicate whether theparticular processed bit combinations are in conformity with the codesystem or not. However, also such a method and checking arrangementwould entail a substantial number of additional components or channelsfor the machine, or would, at least, slow down the operation of themachine.

It is therefore a main object of this invention to pro- 3,091,391Patented May 28, 1963' vide for a method and for an arrangement forchecking in a simple and time-saving manner whether bit combinationsintroduced into or processed by a machine of the type set forth are inconformity with a selected portion of a binary-decimal code system.

It is a further object of this invention to provide for an arrangementof the above purpose which requires a comparatively small number ofchannels, connections and control means for carrying out the checkingoperation.

With the above objects in View, the invention provides for a method ofchecking, in a circuit arrangement for processing digital informationrepresented by signal combinations in terms of a binary-decimalexcess-code, and including checking means, the conformity with such codeof individual signal combinations to be processed, comprising the stepsof introducing such coded digital information into the checking means,and checking on the presence of only those signal combinations containedin said introduced coded information which are needed to indicate bytheir presence that the respective checked inform ation-representingsignal combination is in conformity with the particular code.

In another aspect the invention provides in a circuit arrangement forprocessing digital information represented respectively by bitcombinations in terms of a binarydecimal excess code of n code elements,in combination, input means for receiving digital information andcomprising n input elements respectively assigned to the 11 codeelements, each of said input elements having a first and a second outputfor delivering, respectively, the two different bits alternativelyadapted to constitute the particular code element; a plurality ofAND-circuit rneans respectively assigned to diiferent bit combinationsselected from the binary-decimal excess-code, said AND- circuit meanshaving each a plurality of inputs respectively connected with those ofsaid outputs of said input elements which are assigned to deliver thebits constituting the selected bit combination assigned to therespective AND-circuit means, each of said plurality of AND-circuitmeans, delivering at its output a signal only when from said input meansa bit combination is delivered to said plurality of AND-circuit meanswhich is identical with the selected bit combination assigned to theparticular AND-circuit means; and output means connected with theoutputs of said plurality of AND-circuit means for delivering an outputsignal Whenever any one of said AND-circuit means delivers a signal, sothat the delivery of said output signal indicates that a bit combinationrepresenting digital information in terms of a code of n code elementsand applied to said input means contains the selected bit combinationassigned to at least one of the AND-circuit means, respectively, andtherefore is in conformity with the particular n-element binary-decimalexcess code.

The novel features which are considered as characteristic for theinvention are set forth in particular in the appended claims. Theinvention itself, however, both as to its construction and its method ofoperation together with additional objects and advantages thereof, willbe best understood from the following description of specificembodiments when read in connection with the accompanying drawing, inwhich:

FIG. 1 illustrates diagrammatically a 3-excess code system with 4 codeelements per hit combination and shows which digits between 0 and 9 arerepresented by the various bit combinations;

FIG. 2 illustrates in a similar manner a 27-excess code system composedof bit combinations of 6 code elements, showing also which of the digitsbetween 0 and 9 are represented by the various bit combinations; and

FIG. 3 illustrates diagrammatically a circuit arrangement according tothe invention for carrying out the i 3 method according to the inventionin connection with the use of a code system according to FIG. 2.

The code system illustrated by FIG. 1 is generally known and is a3-excess code system with tour code elements per bit combination. It isderived from a standard 4-element binary code in which 0000 representsby eliminating the first three lines of such a code and by using the bitcombinations which in the regular code would represent the digits from 3to 13 to represent, respectively, the digits ranging from 0 to 9.

The code system according to FIG. 2 is a 6-element binary code which issimilarly derived from a standard 6-element binary code by eliminatingthe first 27 lines of the code and by assigning to each of the digits 0to 9 those bit combinations of the regular code which would in theregular code represent the respective digit plus the digit value 27. Forinstance, the bit combination of FIG. 2 which represents 0 is the samewhich in the regular code would represent 27, and the bit combinationrepresenting according to KG. 2 the digit 3 is the same bit combinationwhich in the regular code would represent 3 plus 27 equal 30.

As can be seen from FIGS. 1 and 2, in an excess-code system two groupsof four bit combinations each comprise partial bit combinations whichare characteristic of the particular group and do not appear in anyother bit combinations of the system. For instance, in the 3-excess codeaccording to FIG. 1 the group of bit combinations representing thedigits 1 to 4 shows in the two highest order positions of code elementsthe partial bit combination 0L, and similarly the group representing thedigits 5 to 8 shows in the same order positions the partial bitcombination L0. In the t27-excess code system according to FIG. 2 thegroup representing the digits from 1 to 4 shows the partial bitcombination OLLL while the group representing the digits from 5 to 8shows the partial bit combination L000. Consequently, according to theinvention (in an n-element code system) an n-element bit combination canbe checked as to whether it represents digits or other information, e.g.alphabetical information, by checking only whether in such a completebit combination is included one of the two partial bit combinationscharacteristic of one or the other of the groups representing the digitvalues 1 to 4, and 5 to 8, while of course the introduced or processedn-element bit combination must be checked separately for the presence ofthe complete bit combinations representing 0 or 9. This means that as awhole only four checks have to be carried out for determiningany'n-element bit combination represents one of the 10 selected digitrepresenting bit combinations of the entire code system.

It can be seen that in this manner the checking on the meaning of codeddigital information is greatly simplified as compared with possibleother methods or means serving the same purpose.

The great advantages of the system according to the invention arestrikingly evidenced by the diagrammatic illustration of an embodimentof an arrangement according to the invention as shown by FIG. 3.

FIG. 3 does not illustrate a circuit diagram for a calculating machine,but only an arrangement for checking the meaning of processedinformation, and this checking arrangement could be combined practicallywith any type of electronic calculating arrangements.

The arrangement according to FIG. 3 has an input section composed of 6input elements respectively corresponding to the 6 code elements whichare the basis of the code illustrated by FIG. 2. By way of example, theinput section may be a shift register of generally known type composedof 6 bistable register elements, e.g. flip-flops FF; to FF Theconsecutive register elements are connected with each other by delaymembers V, as is well known. A -element bit combination which is to bechecked is introduced at the input terminal ZE as 4 a series of pulsesand the thus introduced information is shifted by shift pulses appliedat the shift terminal T in a manner entirely known to the art.

Each of the bistable register elements has, as is known, a first and asecond output which may be also called the normal and complementoutputs. As seen in FIG. 3, the right-hand output of each of theregister elements PR to FF may be considered, for the purpose of weplanation, the normal output at which, when the respective registerelement is in one of its stable states, a signal appears representingthe binary bit L, while no signal appears at this output that wouldrepresent the binary bit 0. The opposite applies to the left-hand output of each of the register elements. Consequently, a bit signal 0 or Lwill be available at one or the other of the outputs of the individualregister elements as indicated in FIG. 3, depending upon the stablestate into which the individual register element has been placed by theintroduction of the 6-element bit combination into the entire shiftregister.

Since, as stated above, only four checks have to be carried out in orderto establish whether a 6-element bit combination applied to the inputmeans is in conformity with the code according to FIG. 2, only fourAND-circuits U M2, M and a are provided in the arrangement, each ofthese AND-circuits having a plurality of inputs which are respectivelyconnected with the first and second outputs of the register elements FFto FF respectively. As is well known, an AND-circuit is capable oftransmitting or delivering a signal only if a signal is applied to allof its inputs. The AND-circuits u and a are assigned to the 6-elementbit combinations representing 0 and 9, respectively, and have for thisreason 6 inputs. The AND-circuits a and u are assigned to the partialbit combinations of four elements only characteristic of the first andsecond group of bit combinations representing digit values from 1 to 4,and from 5 to 8, respectively, and have therefore each four inputs.Consequently, these inputs of the AND-circuits u to 10 respectively,which are intended to receive a binary bit L are connected with theoutput L of that one of the register elements which corresponds by itsposition in the register to the order position of the respective bit Lin the respective AND-circuit. Similarly, those inputs of theAND-circuits which are to receive a binary bit '0, are connected withthe corresponding output of the corresponding register element. Forinstance, in the case of the AND-circuit bi the input M21 is connectedwith the output 0 of the element FF the input 22 is connected with theoutput L of the element FFg, the input 1: is connected with the output Lof the element FF and the output M is connected with the output L of theelement FF Thus, the AND-circuit n is capable of checking on thepresence of the partial fixed combination ()LLL characteristic of thebit combinations representing the digits 1 to 4.

The AND-circuit a serves to check on the presence of the second partialbit combination L000 characteristic of the second group of bitcombinations representing the digits 5 to 8. Therefore the input 1: isconnected with the output L of the element FF the input n is connectedwith the output 0 of the element FF the input M is connected with theoutput 0 of the element FF and the input n is connected with the output0 of the element FF The AND-circuit 1: is assigned to the checking ofthe complete 6-element bit combination representing the digit 0.Consequently its input a is connected with the output 0 of the elementF1 the input u is connected with the output L of the element FF theinput a is connected with the output L of the element PF the input 14 isconnected with the output 0 of the element FF the input 11 is connectedwith the output L of the element FF and the input u is connected withthe output L of the element FP Analogously, the AND-circuit 11 isassigned'to checking on the presence of G-element bit combination moronrepresenting the digit value 9. Therefore, its input 11 is connectedwith the output L of the element FF the input 1: is connected with theoutput of the element FF the input 11 is connected with the output 0 ofthe element FF the input 11 is connected with the output L of theelement FF the input m is connected with the output 0 of the element FFand the input M is connected with the output 0 of the element FP Fromthe above it will be clear that the individual AND-circuits u to 1: willfurnish an output signal only if and when the corresponding bitcombination or partial bit combination has been introduced into theshift register. Any other bit combination, i.e. any bit combination notin conformity with the code system according to FIG. 2, and introducedinto the shift register, will have no effect at the outputs of theAND-circuits M to m.

The output lines u 1: a and 21 of these AND-circuits are connected to acommon OR-circuit 0 which is capable of delivering a signal providedthat any one of the just mentioned output lines carries a signal. Theappearance of a signal at the output of the OR-circuit 0 indicates thatthe 6-element bit combination is introduced into the shift register wasin conformity with the code system according to FIG. 2.

The output of the OR-circuit O is connected with one input of a furtherAND-circuit 1: to other input whereof a check pulse P may be appliedonly after a complete 6- element bit combination has been introducedinto the shift register. When the AND-circuit n is energized both by anoutput pulse from the OR-circuit 0 and by a check pulse P then a signalA would be delivered by the AND- circuit a However, for the purpose ofconvenience, a pulse conversion device I is interposed between the OR-circuit 0 and the first input of the AND-circuit M5. The conversiondevice operates in a well known manner to the effect that if a pulse orsignal is delivered by the OR- eircuit 0 no pulse or signal is deliveredby the conversion device to the AND-circuit n while, when no signal isdelivered by the OR-circuit '0 the conversion device 1 furnishes asignal or pulse to the first input of the AND- circuit a Consequently,upon application of the check pulse P, a warning signal or error signalA will appear at the output of the AND-circuit 11 if the checkingoperation described above indicates that a 6-elernent bit combinationintroduced into the shift register is not in conformity with the codesystem according to FIG. 2.

Summing up, the operation of the arrangement according to FIG. 3 is asfollows. May it be assumed that a bit combination OLLOOO is to bechecked. As can be seen this bit combination is not in conformity withthe excess code according to FIG. 2. This bit combination is introducedas a series of pulses at the input terminal ZE and stored in the shiftregister under the action of the shift pulse applied at the shift inputT. After five shift pulses the entire bit combination will be stored inthe register composed of the flip-flops FF to FP Under thesecircumstances signals will appear at the following outputs of theregister elements: output 0 of FF output L of FF output L of FF output 0of FF,;, output 0 of FF and output 0 of FP As can be easily found by thediagram of FIG. 3, under these circumstances none of the AND-circuits 1:to M}; will obtain signals at all of its inputs and consequently nosignal will be delivered through any one of the output lines u M20, Mand M40, and therefore due to the absence of an output signal, a signalwill .be produced and delivered by the conversion device L. This signalis then applied to the first input of the AND-circuit u The check pulseP should be timed in such a manner that always after a complete 6-element bit combination has been introduced and stored in the shiftregister FF to FP the check pulse P is applied to the AND-circuit a soas to issue an error or warning signal provided that also an outputsignal is delivered from the conversion device I In the present example,such an output signal is delivered by the conversion device J so thatnow the delivery of the error or warning signal indicates that the bitcombination which has been checked is not in conformity with the excesscode.

Had the introduced and checked bit combination been in conformity withthe excess code according to FIG. 2, then an output signal would havebeen applied to the conversion device I and no signal would have beenapplied thereby to the AND-circuit a Consequently upon application ofthe check pulse P no error signal A would have been delivered which factindicates that the checked bit combination was in conformity with theexcess code representing decimal digits.

It is evident, that the error or rwarning signal A appearing in a deviceof any suitable kind as symbolized by the block around the letter Acould as well be utilized for operating for instance a relay in order tocarry out some corrective or other operation in a correspond ing part ofthe machine with which the arrangement according to FIG. 3 is combinedfor cooperation. It can be seen that in operation of the arrangementaccording to FIG. 3 the appearing of a signal A would indicate that theinformation introduced as signals in terms of the binary code is notconstituted by digits represented by the excess-code according to FIG.3, but consists of other eig. alphabetical information represented bysignals in terms of said binary dode.

While for the purpose of explanation in FIG. 3 a shift register has beenshown and described into which the signals representing a bitcombination are introduced in series, it is evident that other types ofregisters or input means may be used as well into which the bitcombination is introduced in parallel.

It will be understood that each of the elements described above or twoor more together, may also find a useful application in other types ofmethod and arrangements for checking the correctness of coded digitalinformation diifering from the types described above.

While the invention has been illustrated and. described as embodied in amethod and arrangement for checking the correctness of digitalinformation represented by a binary-decimal excess-code, it is notintended to be limited to the details shown, since various modificationsand structural changes may be made without departing in any way from thespirit of the present invention.

Without further analysis the foregoing will so fully reveal the gist ofthe present invention that others can by applying current knowledgereadily adapt it for various applications without omitting featuresthat, from the standpoint of prior art, fairly constitute essentialcharacteristics of thegeneric or specific aspects of this invention and,therefore, such adaptations should and are intended to be comprehendedwithin the meaning and range of equivalence of the following claims.

What is claimed and desired to be secured by Letters Patent is:

.1. In a circuit arrangement for processing information data representedrespectively by bit combinations in terms. of a binary code of 11 codeelements, in combination, input means for receiving and storing codedinformation data and comprising n bistable input elements respectivelyassigned to the n code elements, each of said input elements having aninput and a first and a second output for delivering, respectively, thetwo different bits alternatively adapted to constitute the particularcode element; a plurality of AND-circuit means respectively assigned todifferent bit combinations selected from a portion of said binary codeso as to constitute a binarydecimal excess-code representing digitalinformation, said AND-circuit means having each a plurality of inputsrespectively connected with those of said outputs of said input elementswhich are assigned to deliver the bits. con-- stituting the selectedbitcombination assigned to the respective AND-circuit means, each of saidplurality of AND-circuit means deliverin-g at its output a signal onlywhen from said input means a bit combination is delivered to saidplurality of AND-circuit means which is identical with the selected bitcombination assigned to the particular AND-circuit means; output meansconnected with the outputs of said plurality of AND-circuit means forstoring an output signal whenever any one of said AND-circuit meansdelivers a signal and for delivering said output signal upon applicationthereto of a release signal; and means for applying a release signal tosaid output means, so that the delivery of said output signal indicatesthat a bit combination representing information data in terms of a codeof 11 code elements and applied to said input means contains theselected bit combination assigned to at least one of the AND-circuitmeans, respectively, and therefore is in conformity with that portion ofthe particular n-element code which constitutes a binary-decimal excesscode representing digital information.

2. In a circuit arrangement for processing information data representedrespectively by bit combinations in terms of a binary code of n codeelements, in combination, shift register means for receiving and storingcoded information data and comprising n bistable register elementsrespectively assigned to the n code elements and delay elementsconnected between consecutive register elements, each of said registerelements having an input and a first and a second output for delivering,respectively, the two different bits alternatively adapted to constitutethe particular code element; a plurality of AND-circuit meansrespectively assigned to different bit combinations selected from aportion of said binary code so as to constitute a binary-decimal excesscode representing digital information, said AND-circuit means havingeach a plurality of inputs respectively connected with those of saidoutputs of said register elements which are assigned to deliver the bitsconstituting the selected bit combination assigned to the respectiveAND-circuit means, each of said plurality of AND-circuit meansdelivering at its output a signal only when by said register means a bitcombination is delivered to said plurality of AND-circuit means which isidentical with the selected bit combination assigned to the particularAND-circuit means; and output means connected with the outputs of saidplurality of AND-circuit means for storing an output signal whenever anyone of said AND-circuit means delivers a signal and for delivering saidoutput signal upon application thereto of a release signal; and meansfor applying a release signal to said output means, so that the deliveryof said output signal indicates that a bit combination representinginformation data in terms of a code of n code elements and applied tosaid register means contains a selected bit combination assigned to atleast one of the AND-circuit means, respectively, and therefore is inconformity with that portion of the particular n-element code whichcontributes a binary-decimal excess code representing digitalinformation.

3. In a circuit arrangement for processing information data representedrespectively by bit combinations in terms of a binary code of n codeelements, in combination, shift register means for receiving and storingcoded information data and comprising n bistable register elementsrespectively assigned to the n code elements and delay elementsconnected between consecutive register elements, each of said registerelements having an input and a first and a second output for delivering,respectively, the two different bits alternatively adapted to constitutethe particular code element; a plurality of AND-circuit meansrespectively assigned to different bit combinations selected from aportion of said binary code so as to constitute a binary-decimal excesscode representing digital information, said AND-circuit means havingeach a plurality of inputs respectively connected with those of saidoutputs of said register elements which are assigned to deliver the bitsconstituting the selected bit combination assigned to, the respectiveAND-circuit means, each of said plurality of AND-circuit meansdelivering at its output a signal only when from said register means abit combination is delivered to said plurality of AND-circuit meanswhich is identical with the selected bit combination assigned to theparticular AND-circuit means; output means including OR-circuit meansconnected with the outputs of said plurality of AND-circuit means forstoring an output signal whenever any one of said AND-circuit meansdelivers a signal and for delivering said output signal upon applicationthereto of a release signal; and means for applying a release signal tosaid output means, so that the delivery of said output signal indicatesthat a bit combination representing information data in terms of a codeof n code elements and applied to said register means contains aselected bit combination assigned to at least one of the AND-circuitmeans, respectively, and therefore is in conformity with that portion ofthe particular n-element code which constitutes a binary-decimal excesscode representing digital information.

4. In a circuit arrangement for processing information data representedrespectively by bit combinations in terms of a binary code of 12 codeelements, in combination, shift register means for receiving and storingcoded information data and comprising n bistable register elementsrespectively assigned to the 11 code elements and delay elementsconnected between consecutive register elements, each of said registerelements having an input and a first and a second output for delivering,respectively, the two different bits alternatively adapted to constitutethe particular code element; a plurality of AND-circuit meansrespectively assigned to different bit combinations selected from aportion of said binary code so as to constitute a binary-decimal excesscode representing digital information, said AND-circuit means havingeach a plurality of inputs respectively connected with those of saidoutputs of said register elements which are assigned to deliver the bitsconstituting the selected bit combination assigned to the respectiveAND-circuit means, each of said plurality of AND-circuit meansdelivering at its output a signal only when from said register means abit combination is delivered to said plurality of AND-circuit meanswhich is identical with the selected bit combination assigned to theparticular AND-circuit means; output means including OR-circuit meansconnected with the outputs of said plurality of AND-circuit means forstoring an output signal whenever any one of said AND-circuit meansdelivers a signal and for delivering said output signal upon applicationthereto of a release signal, said output means further including anAND-circuit arrangement connected at one input with said OR-circuitmeans, and at another input with an outside pulse source, for deliveringan indicating signal upon simultaneous energization of said AND-circuitarrangement by said output signal and said outside pulse; and an outsidepulse source for energizing said AND-circuit by application of saidrelease signal, so that the delivery of said indicating signal indicatesthat a bit combination representing information data in terms of a codeof 11 code elements and applied to said register mean-s contains aselected bit combination assigned to at least one of the AND-circuitmeans, respectively, and therefore is in conformity with that portion ofthe particular n-element code which constitutes a binary-decimal excesscode representing digital information.

5. An arrangement as claimed in claim 4 wherein conversion means areinterposed between said OR-circuit means and said AND-circuitarrangement, said conversion means providing a signal energizing saidAND-circuit arrangement when no output signal is delivered by sm'dOR-circuit means, and said conversion means providing no signal forenergizing said AND-circuit arrangement when an output signal isdelivered by said OR-circuit means, so that said indicating signal, whendelivered, will indicate that no signal is delivered by any one of saidAND-circuit means because the particular bit combination applied to saidregister means is not in conformity with that portion of the particularcode which constitutes a binary-excess code representing digitalinformation.

6. In a circuit arrangement for processing information data representedrespectively by bit combinations in terms of a binary code of n codeelements, in combination, input means for receiving and storing codedinformation data and comprising n bistable input elements respectivelyassigned to the n code elements and delay elements connected betweenconsecutive register elements, each of said input elements having aninput and a first and a second output for delivering, respectively, thetwo different b-its alternatively adapted to constitute the particularcode element; four AND-circuit means respectively assigned to fourdifferent bit combinations selected from a portion of said binary codeso as to constitute a binarydecimal excess code representing digitalinformation, two of said selected bit combination-s representin thedigit values and 9, respectively, one of the two other ones of saidselected bit combinations being parts of n-element bit combinationsaccording to said binary-decimal excess code rep-resenting digitsranging between 1 and 4 and being a common characteristic thereof, andthe remaining one of said selected bit combinations being parts ofnelement bit combinations according to said binary-decimal excess coderepresenting digit values ranging between 5 and 8 and beingcharacteristic thereof, said AND-circuit means having each a pluralityof inputs respectively connected with those of said outputs of saidinput elements which are assigned to deliver the bits constituting theselected bit combination assigned to the respective AND- circuit means,each of said plurality of AND-circuit means delivering at its output asignal only when from said input means a bit combination is delivered tosaid plurality of AND-circuit means which is identical with the selectedbit combination assigned to the particular AND-circuit means; outputmeans connected with the outputs of said plurality of AND-circuit meansfor storing an output signal whenever any one of said AND-circuit meansdelivers a signal and for delivering said output signal upon applicationthereto of a release signal; and means for applying a release signal tosaid output means, so that the delivery of said output signal indicatesthat a bit combination representing information data in terms of a codeof 11 code elements and applied to said input means contains a selectedbit combination assigned to at least one of the AND-circuit means,respectively, and therefore is in conformity with that portion of theparticular n-element code which constitutes a binary-decimal excess coderepresenting digital information.

7. In a circuit arrangement for processing information data representedrespectively by bit combinations in terms of a binary code of 11 codeelements, in combination, shift register means for receiving and storingcoded information and comprising n bistable register elementsrespectively assigned to the n code elements and delay elementsconnected between consecutive register elements, each of said registerelements having an input and a first and a second output for delivering,respectively, the two differcut bits alternatively adapted to constitutethe particular code element; four AND-circuit means respectivelyassigned to four ditferent bit combinations selected from a portion ofsaid binary code so as to constitute a binarydecimal excess coderepresenting digital information, two of said selected bit combinationsrepresenting the digit values 0 and 9, respectively, one of the twoother ones of said selected bit combinations being parts of n-elementbit combinations according to said binary-decimal excess coderepresenting digits ranging between 1 and 4- and being a commoncharacteristic thereof, and the remaining one of said selected bitcombinations being parts of nelement bit combinations according to saidbinary-decimal excess code representing digit values ranging between 5and 8 and being characteristic thereof, said AND-circuit means havingeach a plurality of inputs respectively connected with those of saidoutputs of said register elements which are assigned to deliver the bitsconstituting the selected bit combination assigned to the respectiveAND- circuit means, each of said plurality of AND-circuit meansdelivering at its output a signal only when from said register means abit combination is delivered to said plurality of AND-circuit meanswhich is identical with the selected bit combination assigned to theparticular AND- circuit means; output means including OR-circuit meansconnected with the outputs of said plurality of AND- circuit means forstoring an output signal whenever any one of said AND-circuit meansdelivers a signal and for delivering said output signal upon applicationthereto of a release signal, said output means :further including anAND-circuit arrangement connected at one input with said OR-circuitmeans, and at another input with an outside pulse source, for deliveringan indicating signal upon simultaneous energization of said AND-circuitarrangement by said output signal and said outside pulse; and an outsidepulse source for energizing said AND-circuit by application of saidrelease signal, so that the delivery of said indicating signal indicatesthat a bit combination representing information data in terms of a codeof 11 code elements and applied to said register means contains aselected bit combination assigned to at least one of the AND-circuitmeans, respectively, and therefore is in conformity with that portion ofthe particular n-element code which constitutes a binary-decimal excesscode representing digital information.

8. An arrangement as claimed in claim 1, wherein said bistable inputelements are bistable flip-flop circuits.

9. An arrangement as claimed in claim 1, wherein said output meansinclude control means actuatable by said output signal and adapted to beconnected with another machine means so as to cause the latter, whensaid control means is actuated, to process said information data storedin said input means.

Randlev: A Method to Determine at the Source the Validity of TransmittedSignals, I.B.M. Technical Disclosure Bulletin, vol. 2, No. 5, February1960, 2 pp.

6. IN A CIRCUIT ARRANGEMENT FOR PROCESSING INFORMATION DATA REPRESENTEDRESPECTIVELY BY BIT COMBINATION IN TERMS OF A BINARY CODE OF N CODEELEMENTS, IN COMBINATION, INPUT MEANS FOR RECEIVING AND STORING CODEDINFORMATION DATA AND COMPRISING N BISTABLE INPUT ELEMENTS RESPECTIVELYASSIGNED TO THE N CODE ELEMENTS AND DELAY ELEMENTS CONNECTED BETWEENCONSECUTIVE REGISTER ELEMENTS, EACH OF SAID INPUT ELEMENTS HAVING ANINPUT AND A FIRST AND A SECOND OUTPUT FOR DELIVERING, RESPECTIVELY, THETWO DIFFERENT BITS ALTERNATIVELY ADAPTED TO CONSTITUTE THE PARTICULARCODE ELEMENT; FOUR AND-CIRCUIT MEANS RESPECTIVELY ASSIGNED TO FOURDIFFERENT BIT COMBINATIONS SELECTED FROM A PORTION OF SAID BINARY CODESO AS TO CONSTITUTE A BINARYDECIMAL EXCESS CODE REPRESENTING DIGITALINFORMATION, TWO OF SAID SELECTED BIT COMBINATIONS REPRESENTING THEDIGIT VALUES 0 AND 9, RESPECTIVELY, ONE OF THE TWO OTHER ONES OF SAIDSELECTED BIT COMBINATIONS BEING PARTS OF N-ELEMENT BIT COMBINATIONSACCORDING TO SAID BINARY-DECIMAL EXCESS CODE REPRESENTING DIGITS RANGINGBETWEEN 1 AND 4 AND BEING A COMMON CHARACTERISTIC THEREOF, AND THEREMAINING ONE OF SAID SELECTED BIT COMBINATIONS BEING PARTS OF NELEMENTBIT COMBINATIONS ACCORDING TO SAID BINARY-DECIMAL EXCESS CODEREPRESENTING DIGIT VALUES RANGING BETWEEN 5 AND 8 AND BEINGCHARACTERISTIC THEREOF, SAID AND-CIRCUIT MEANS HAVING EACH A PLURALITYOF INPUTS RESPECTIVELY CONNECTED WITH THOSE OF SAID OUTPUTS OF SAIDINPUT ELEMENTS WHICH ARE ASSIGNED TO DELIVER THE BITS CONSTITUTING THESELECTED BIT COMBINATION ASSIGNED TO THE RESPECTIVE ANDCIRCUIT MEANS,EACH OF SAID PLURALITY OF AND-CIRCUIT MEANS DELIVERING AT ITS OUTPUT ASIGNAL ONLY WHEN FROM SAID INPUTS MEANS A BIT COMBINATION IS DELIVEREDTO SAID PLURALITY OF AND-CIRCUIT MEANS WHICH IS IDENTICAL WITH THESELECTED BIT COMBINATION ASSIGNED TO THE PARTICULAR AND-CIRCUIT MEANS;OUTPUT MEANS CONNECTED WITH THE OUTPUTS OF SAID PLURALITY OF AND-CIRCUITMEANS FOR STORING AN OUTPUT SIGNAL WHENEVER ANY ONE OF SAID AND-CIRCUITMEANS DELIVERS A SIGNAL AND FOR DELIVERING SAID OUTPUT SIGNAL UPONAPPLICATION THERETO OF A RELEASE SIGNAL; AND MEANS FOR APPLYING ARELEASE SIGNAL TO SAID OUTPUT MEANS, SO THAT THE DELIVERY OF SAID OUTPUTSIGNAL INDICATES THAT A BIT COMBINATION REPRESENTING INFORMATION DATA INTERMS OF A CODE OF N CODE ELEMENTS AND APPLIED TO SAID INPUT MEANSCONTAINS A SELECTED BIT COMBINATION ASSIGNED TO AT LEAST ONE OF THEAND-CIRCUIT MEANS, RESPECTIVELY, AND THEREFORE IS IN CONFORMITY WITHTHAT PORTION OF THE PARTICULAR N-ELEMENT CODE WHICH CONSTITUTES ABINARY-DECIMAL EXCESS CODE REPRESENTING DIGITAL INFORMATION.